This invention relates generally to fabrication of semiconductor devices, and more particularly, to an apparatus and a method for applying two dimensional very large scale integration (VLSI) circuit design techniques to a three-dimensional device.
Conventional integrated circuits, or "chips," are formed from two dimensional or flat surface semiconductor wafers. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and it is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface using various design concepts, such as VLSI circuit design. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
A fabrication facility is relatively expensive due to the enormous effort and expense required for creating flat silicon wafers and chips. For example, manufacturing the wafers requires several high-precision steps including creating rod-form polycrystalline semiconductor material; precisely cutting ingots from the semiconductor rods; cleaning and drying the cut ingots; manufacturing a large single crystal from the ingots by melting them in a quartz crucible; grinding, etching, and cleaning the surface of the crystal; cutting, lapping, and polishing wafers from the crystal; and heat processing the semiconductor wafers. Moreover, the wafers produced by the above processes typically have many defects which are largely attributable to the difficulty in making a single, highly pure crystal due to the above cutting, grinding, and cleaning processes as well as due to the impurities, including oxygen, associated with containers used in forming the crystals. These defects become more and more prevalent as the integrated circuits formed on these wafers become smaller.
Another major problem associated with modem fabrication facilities for flat chips is that they require extensive and expensive equipment. For example, dust-free clean rooms and temperature-controlled manufacturing and storage areas are necessary to prevent the semiconductor wafers and chips from defecting and warping. Also, these types of fabrication facilities suffer from a relatively inefficient throughput as well as an inefficient use of the silicon. For example, facilities using in-batch manufacturing, where the wafers are processed by lots, must maintain huge inventories to efficiently utilize all the equipment of the facility. Also, because the wafers are round disks, and the completed chips are rectangular, the peripheral portion of each semiconductor wafer cannot be used.
Still another problem associated with modern fabrication facilities is that they do not produce chips that are ready to use. Instead, there are many additional steps that must be completed, including cutting and separating the chip from the wafer; assembling the chip to a lead frame which includes wire bonding, plastic or ceramic molding, cutting and forming the leads, positioning the assembled chip onto a printed circuit board, and mounting the assembled chip to the printed circuit board. The cutting and assembly steps introduce many errors and defects due to the precise requirements of such operations. In addition, the positioning and mounting steps are naturally two-dimensional in character, and therefore cannot be applied to circuit designs on curved or three-dimensional areas.
Specifically, circuits on flat chips are designed using two-dimensional computer aided circuit design tools. However, these conventional circuit design tools for VLSI circuitry design are not suitable for three-dimensional surfaces. Therefore, what is needed is an apparatus and a method for producing a mask for creating circuit designs on three-dimensional surfaces using two-dimensional circuit design tools.